october 1998 ml2037 * 500khz, serial input, programmable sine wave generator with digital gain control general description the ml2037 is a precision programmable sine wave generator with a frequency range of dc to 500khz. the device is capable of generating a wide frequency range of low distortion sine waves with no external passive components. the frequency of the sine wave output is programmed by a 16-bit word that is loaded through a serial input. the sine wave output frequency is determined by the programmed value and the clock frequency. the clock frequency is derived from either an external crystal connected to the device or an external clock input to provide a stable and accurate frequency reference. the sine wave output of the ml2037 is filtered and has a programmable amplitude that is digitally programmed in 0.5v steps. the maximum amplitude is 2.0v p-p centered at a 2.5v level. the device functions from a single 5v power supply and has a shutdown pin to put the device into a low power mode that disables the output. a sync input is provided to allow the synchronization of more than one device in a system. block diagram features programmable output frequency: dc to 400khz?sing a crystal dc to 500khz?sing an external digital clock 3-wire spi compatible serial interface with double buffered latch for programming the frequency digital gain control for programming output amplitude sync input for synchronization of multiple sine waves shutdown pin for sleep mode single 5v power supply operation av cc 12 d gnd d gnd out s enable s clk s data in 7 4 6 10 8-bit dac gain control & smoothing filter g0 14 g1 15 reference phase accumulator 512 point sine look-up table 8 16 16 16-bit data latch 16-bit shift register crystal oscillator 2 clk in 13 clk out 3 av cc 11 dv cc 16 sync 2 agnd 9 shdn 8 1 5 * this part is end of life as of august 1, 2000 rev. 1.0 10/10/2000
ml2037 2 rev. 1.0 10/10/2000 pin configuration pin description pin name function 1, 5 d gnd ground connection for the digital sections of the ic. 2 sync synchronization input. holding this pin low stops the sine wave output, and resets the phase to zero. 3 clk out output of the internal high frequency clock generator. f clk out = ?f clk in . 4 s clk serial data clock input. serial data is clocked into the shift register on falling edges of s clk. 6 s data in serial data input for programming the output frequency. 7 s enable serial interface enable control. a logic high on this pin allows data to be entered into the latch. 8 shdn a logic high on this pin causes the output of the generator to shut off and places the ic in a low power standby mode. pin name function 9 a gnd ground reference for analog sections of the ic and reference for out. 10 out sine wave output. the amplitude of the sine wave will vary around a 2.5v dc level. 11,12 av cc power supply for the analog sections of the ic. 13 clk in input of the internal high frequency clock generator. this pin is either driven from an external clock input or connected to a crystal for use with the internal oscillator. 14 g0 output gain control. works with g1 to set the output amplitude to one of four different full scale ranges. 15 g1 output gain control. works with g0 to set the output amplitude to one of four different full scale ranges. 16 dv cc power supply for the digital sections of the ic. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 d gnd sync clk out s clk d gnd s data in s enable shdn dv cc g1 g0 clk in av cc av cc out a gnd top view ml2037 16-pin pdip (p16) 16-pin wide soic (s16w)
ml2037 rev. 1.0 10/10/2000 3 electrical characteristics unless otherwise specified, av cc = dv cc = 4.75v to 5.25v, shdn = 0v, clk in = 25.6mhz (crystal) or 32mhz (external clock), c l = 50pf, r l = 1k ? , t a = operating temperature range (note 1) symbol parameter conditions min typ max units output hd harmonic distortion 20hz to 31.25khz -45 db (2nd and 3rd harmonic) 31.25khz to 500khz -40 db snd signal to noise + distortion 1khz to 31.25khz, -45 db f out bw < 31.25khz 31.35khz to 500khz, -40 db f out bw < 500khz gain error f out <125khz, c suffix 0.15 db av cc = 5v, g1=1, g0=1 f out <125khz, i suffix 0.25 db av cc = 5v, g1=1, g0=1 125khz ml2037 4 rev. 1.0 10/10/2000 note 1: limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. electrical characteristics (continued) symbol parameter conditions min typ max units oscillator (continued) t r clk out rise time c l = 25pf, see timing diagram 2 8 ns t f clk out fall time c l = 25pf, see timing diagram 2 8 ns logic v il input low voltage 1.0 v v ih input high voltage dv cc - 1 v i il input low current -1 a i ih input high current 1 a v ol output low voltage i ol = -2ma 0.4 v v oh output high voltage i oh = 2ma 4.0 v f s clk serial clock frequency 0.01 10 mhz t pw serial clock pulse width 40 ns t ssd s data in setup time 10 ns t hsd s data in hold time 10 ns t ssens s enable setup time 30 ns t ssenh s enable hold time 50 ns t dsen delay from s enable to stable output f clk in = 32mhz 500 ns t dsync delay from sync to output start f clk in = 32mhz 500 ns supply ai cc av cc current f clk in = 16mhz 35 45 ma f clk in = 32mhz 40 50 ma shdn = 5v 10 a di cc dv cc current f clk in = 16mhz 10 14 ma f clk in = 32mhz 16 20 ma shdn = 5v 30 a f clk out f clk in t r t f clk in clk out timing diagram 1. timing diagram 2. t ssens t ssenh s clk s data in s enable t ssd t hsd t pw t pw d0 d1 d2 d14 d15
ml2037 rev. 1.0 10/10/2000 5 functional description the ml2037 is composed of a programmable frequency generator, a sine wave generator, a crystal oscillator, and a digital interface. the functional block diagram is shown in figure 1. programmable frequency generator the programmable frequency generator produces a digital output whose frequency is determined by a 16-bit digital word. the frequency generator is composed of a phase accumulator which is clocked at ?f clk in . the value stored in the data latch is added to the phase accumulator every two cycles of clk in. the frequency of the analog output is equal to the rate at which the accumulator overflows and is given by the following equation: (1) where (d15?0) is the decimal value of the programming word. the frequency resolution and the minimum frequency are the same and can be calculated using: (2) when f clk in = 25mhz, ? f min = 5.96hz ( 2.98hz). lower output frequencies are obtained by using a lower clock frequency. the maximum frequency output can be easily calculated with the following equation: (3) when f clk in = 25mhz, f out(max) = 391khz. higher frequencies, up to 500khz, are obtained by using an external clock, where 25mhz < f clk in < 32mhz. due to the phase quantization nature of the frequency generator, spurious tones can be present in the output in the range of ?0db relative to fundamental. the energy from these tones is included in the signal to noise + distortion specification (snd) given in the electrical table. the frequency of these tones can be very close to the fundamental, and it is not practical to filter them out. sinewave generator the sinewave generator is composed of a sine lookup table, an 8-bit dac, an output smoothing filter, and an amplifier. the sine lookup table is addressed by the phase accumulator. the dac is driven by the output of the table and generates a staircase representation of a sine wave. the output filter smooths the analog output by removing the high frequency sampling components. the resultant voltage on v out is a sinusoid with the second and third harmonic distortion components at least 40db below the fundamental. the ml2037 has a 2-bit (g1, g0) digital gain control. with the gain input equal to logic 00, the sine wave amplitude is equal to 0.5v p-p . incrementing the gain control input increases the output amplitude in 0.5v steps to a maximum of 2.0v p-p . the output amplitude is accurate to within 0.5db over the frequency range. g1 g0 p? output amplitude 0 0 .5v 0 1 1.0v 1 0 1.5v 1 1 2.0v the analog section is designed to operate over a frequency range of dc to 500khz and is capable of driving 1k ? , 50pf loads at the maximum amplitude of 2.0v p-p . the sine wave output is typically centered about a 2.5v dc level, so for a 2v p-p sine wave, the output will swing from 1.5v to 3.5v. crystal oscillator the crystal oscillator generates an accurate reference clock for the programmable frequency generator. the internal clock can be generated with a crystal or external clock. if a crystal is used, it must be placed between clk in and dgnd. an on-chip oscillator will then generate the internal clock. no other external components are required. the crystal should be a parallel resonant type with a frequency between 5mhz to 25.6mhz. it should be placed physically as close as possible to clk in and dgnd, to minimize trace lengths. the crystal must have the following characteristics: parallel resonant type frequency: 5mhz to 25.6mhz maximum esr: 120 ? @ 5 to 10mhz, 80 ? @10 to 15mhz, and 50 ? @ 15 to 25.6mhz drive level: 500 w typical load capacitance: 18 - 20pf maximum case capacitance: 7pf the frequency of oscillation will be a function of the crystal parameters and board capacitance. in general, f f f min clkin 2 22 f f out max clkin () 2 6 f clkin (d15 d0) dec out = = = 2 22 ?
ml2037 6 rev. 1.0 10/10/2000 16-bit shift register 16-bit data latch 21-bit adder a 16 a 0 a 20 a 15 b 0 b 20 21-bit latch sum (21 bits) q 20 q 0 binary phase accumulator f ref quadrant complementer least significant (12 bits) phase samples (7 bits) sign bit quadrant bit (16 bits) (16 bits) input to quadrant complementor t = 1 f ref input to rom pictorial presentation of digital data input to sign complementor sign bit (7 bits) read-only memory (128 x 7) (7 bits) (7 bits) (7bits) sign complementor output latch 8-bit digital-to-analog converter gain control & low-pass filter sinewave output output of low-pass filter (analog signal) input to low-pass filter (analog signal) input to d/a converter input to output latch sign bit sign bit f ref clk in crystal oscillator 2 s enable s data in g1 g0 figure 1. detailed block diagram of the ml2037.
ml2037 rev. 1.0 10/10/2000 7 microprocessor crystals meet the above requirements, but it is recommended to test the selected crystal in circuit to insure proper operation. suitable crystals can be purchased from the following suppliers: ecs, inc. fox electronics m-tron industries an external clock can drive clk in directly if desired. the frequency of this clock can be anything from 0 to 32mhz. however, at clock frequencies below 5mhz, the sine wave output begins to exhibit "staircasing". the ml2037 has a clock output that can be used to drive other external devices. the clk out output is a buffered output from the oscillator which runs at one half the frequency of clk in. serial digital interface the digital interface consists of a shift register and data latch. the serial 16-bit data word on s data in is clocked into a 16-bit shift register on falling edges of the serial shift clock, s clk. the lsb should be shifted in first and the msb last as shown in timing diagram 1. the data that has been shifted into the shift register is loaded into a 16- bit data latch on the falling edge of s enable. to insure that true data is loaded into the data latch from the shift register, the s enable falling edge should occur before the s clk transitions high to low. s enable should be high while shifting data into the shift register. note that all data is entered and latched on edges, not levels, of s clk and s enable. upon power up, the data in the latch is indeterminate. it is therefore recommended to initialize the frequency data as part of a power up routine. functional description (continued) synchronization when the sync pin is held high, the sine wave generator operates normally. pulling this pin low causes the sine wave output to be interrupted and resets the phase back to zero. the sine wave output goes to the 2.5v dc level approximately 1 s after the sync input goes low. switching the sync pin back to a high level starts the sine wave going again from zero phase. the delay from when the sync goes high to the start of the sine wave is about 500ns, as shown in figure 2. if several generator chips are driven from the same clock, the sync input allows them to be phase synchronized to any value. figure 3 gives an example of how a microcontroller can be used with two ml2037s to generate two sine waves that are 90 out of phase. shutdown the shdn input provides a means to power down the analog section and the internal clock of the sine wave generator. when in the power down mode the part will draw only 10 a of input current and the output will go to zero approximately 500ns after the shdn pin goes high. switching the shdn back to a low level allows the sine wave to resume at the last programmed frequency. the delay from when the shdn goes low to when the sine wave resumes is about 200 s. the use of the power down mode allows power management for portable applications or for gating the internal oscillator for low noise applications. power supplies the analog circuitry in the device is powered from 5v (av cc ) and is referenced to agnd. the digital circuits in the device can also powered from the same 5v supply (dv cc to dgnd). it is recommended that agnd and dgnd be connected together close to the device and have a good connection back to the power source. it is recommended that the power supplies to the device should be bypassed by placing decoupling capacitors from av cc to agnd and dv cc to dgnd as physically close to the device as possible. figure 2. sync pin timing. 1 s snyc 500ns out
ml2037 8 rev. 1.0 10/10/2000 figure 3. synchronizing two ml2037 sine wave generators. controller clk in s data in s clk s enable sync clk in s data in s clk s enable sync out out clock oscillator ml2037 ml2037
ml2037 rev. 1.0 10/10/2000 9 physical dimensions inches (millimeters) seating plane 0.240 - 0.260 (6.09 - 6.61) pin 1 id 0.295 - 0.325 (7.49 - 8.26) 0.740 - 0.760 (18.79 - 19.31) 0.016 - 0.022 (0.40 - 0.56) 0.100 bsc (2.54 bsc) 0.008 - 0.012 (0.20 - 0.31) 0.015 min (0.38 min) 16 0 - 15 1 0.055 - 0.065 (1.40 - 1.65) 0.170 max (4.32 max) 0.125 min (3.18 min) 0.02 min (0.50 min) (4 places) package: p16 16-pin pdip seating plane 0.291 - 0.301 (7.39 - 7.65) pin 1 id 0.398 - 0.412 (10.11 - 10.47) 0.400 - 0.414 (10.16 - 10.52) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.022 - 0.042 (0.56 - 1.07) 0.095 - 0.107 (2.41 - 2.72) 0.005 - 0.013 (0.13 - 0.33) 0.090 - 0.094 (2.28 - 2.39) 16 0.009 - 0.013 (0.22 - 0.33) 0 - 8 1 0.024 - 0.034 (0.61 - 0.86) (4 places) package: s16w 16-pin wide soic
ml2037 10 rev. 1.0 10/10/2000 ordering information part number temperature range package ml2037cp (obs) 0 c to 70 c 16-pin pdip (p16) ML2037CS (obs) 0 c to 70 c 16-pin wide soic (s16w) ml2037ip (obs) -40 c to 85 c 16-pin pdip (p16) ml2037is (eol) -40 c to 85 c 16-pin wide soic (s16w) life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ?2000 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
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